Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow is hardware description language (HDL) compilation. HDL compilation involves performing synthesis, placement, routing, and timing analysis of the system on the target device.
Functional verification is a procedure that may also be performed during HDL compilation by EDA tools. Functional verification is used to ensure the functional correctness of implemented circuits. When used, more than 70% of a design cycle may be spent performing functional verification. Techniques that may be used for functional verification include simulation and formal verification. Simulation is typically used to verify the correctness of Register-Transfer-Level (RTL) circuit description against design intent. Constrained random simulation is a technique that may be used to reduce simulation time and to increase functional coverage efficiency. Constrained random simulation has been shown to be effective in identifying bugs early in a design cycle. Once RTL is implemented using EDA tools, formal verification may be used to verify the correctness of a circuit against the RTL description. Formal verification can be a computationally difficult problem to solve as it seeks to mathematically prove that the two circuits being compared have identical functional behavior. To cope with this complexity, some formal verification techniques and tools in the industry are combinational verification tools. Combinational verification tools use primary outputs and register boundaries as compare points for the two circuits being compared for equivalency.